The present invention relates to a boundary-scan circuit, and more particularly to a boundary-scan circuit that selects between a system clock signal received by a clock pin of an electronic device and a test clock signal.
The semiconductor industry has adopted IEEE Std. 1149.1 (1990), which is hereby incorporated by reference, in order to provide a standard test architecture. The intent of the IEEE Std. 1149.1 standard is to provide compatibility of test control and data signals between devices from different manufacturers in much the same way that compatibility within a logic family, e.g. TTL, CMOS, etc., presently exists. This standard test architecture facilitates the development of standard tests and standard test development techniques.
The standard architecture has provisions for numerous types of testing. Boundary-scan testing and built-in-self-test (BIST) testing are two of the commonly used provisions. During both boundary-scan testing and BIST testing the circuit under test often is controlled by timing pulses from a test clock, rather than the normal pulses from a system clock. Thus, the electronic device must have some type of circuit that changes from the system clock signal pulses and to test clock signal pulses during a boundary-scan or BIST test.
In normal operation, the system clock is typically received by each electronic device, e.g. an ASIC or a PLA, via a clock input pin. During a test the test clock is used for all or a portion of the test and the system clock is disconnected from the circuit unless a portion of the test requires the use of the system clock.
A problem arises, though, as the circuit under test is switched from the system clock to the test clock. The problem occurs whenever the control signal that causes the switch from the system clock to the test clock switches while one or both of the clock signals are changing states. Switch over during such a time often causes the occurrence of undesirable pulses which cause uncertain and erratic results from the circuit under test. Any switching in the time region of a logic transition of one of the clock signals can cause one or more short pulses which are too short in duration and/or amplitude to properly qualify as logic pulses. Such pulses lead to metastable oscillations in cross coupled devices and uncertain responses from other types of logic devices. Additionally, the uncertainty of the response by the circuit under test may be exacerbated by current loading of the clock switching device, which loading detrimentally affects the rise time and amplitude of short pulses.
A very similar problem of undesirable pulses arises when the circuit under test switches back from the test clock signal to the system clock signal to resume normal operation of the circuit.
Thus, it is an object of the present invention to provide a boundary-scan circuit clock input circuit that switches from a system clock signal to a test clock signal without causing undesirable pulses that cause metastable oscillations and uncertain responses in core logic circuits.
It is another object of the present invention to provide a boundary-scan circuit clock input circuit that switches from a test clock signal to a system clock signal without causing undesirable pulses that cause metastable oscillations and uncertain responses in core logic circuits.